VLSI Online Training

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VLSI Online Training


 (4.9) | 350 Ratings


Introduction


VLSI Online Training Details
Track Regular Track Weekend Track Fast Track
Course Duration 30 Hrs 8 Weekends 5 Days
Hours 1hr/day 2 Hours a day 6 Hours a day
Training Mode Online Classroom Online Classroom Online Classroom
Delivery Instructor Led-Live Instructor Led-Live Instructor Led-Live


Course Curriculum

VLSI Online Training Introduction

ASIC / FPGA DESIGN

ASIC / FPGA Design Fundamentals

Advanced Digital Design

CMOS

  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

VHDL

  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Enumerated Data Types
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • If-then-else, Case
  • Slicing and Concatenation
  • Loop Statements
  • Delta Delay Concept
  • Arrays, Memory Modeling, FSM
  • Writing Procedures
  • Writing Functions
  • Behavioral / RTL Coding
  • Operator Overloading
  • Structural Coding
  • Component declarations and installations
  • Generate Statement
  • Configuration Block
  • Libraries, Standard packages
  • Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Assertion based verification
  • Files read and write operations
  • Code for complex FPGA and ASICs
  • Generics and Generic maps

VERILOG

  • Language introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, for-each, repeat
  • Combination and sequential circuit designs
  • Memory modeling,, state machines
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Assertion based verification
  • Code for synthesis
  • Advanced topics
  • Writing reusable code

System Verilog

  • Introduction to System Verilog
  • System Verilog Declaration spaces
  • System Verilog Literal Values and Built-in Data Types
  • System Verilog User-Defined and Enumerated Types
  • System Verilog Arrays, Structures and Unions
  • System Verilog Procedural Blocks, Tasks and Function
  • System Verilog Procedural Statements
  • Modelling Finite State Machines with System Verilog
  • System Verilog Design Hierarchy
  • System Verilog Interfaces
  • Behavioral and Transaction Level Modelling
  • FPGA Flow
  • Re-configurable Devices, FPGA’s/CPLD’s
  • Architectures of XILINX, ALTERA Devices
  • Designing with FPGAs
  • FPGA’s and its Design Flows
  • Architecture based coding
  • Efficient resource utilization
  • Constrains based synthesis
  • False paths and multi cycle paths
  • UCF file creation
  • Timing analysis/Floor Planning
  • Place and route/RPM
  • Back annotation, Gate level simulation, SDF Format
  • DSP on FPGA
  • Writing Scripts
  • Hands on experience with industry Standard Tools
  • ASIC Flow

Projects: As a part of course 2 mini projects and 1 major project

  • EDA Tools / CAD Flow for IC Design
  • Simulation/Synthesis using ASIC libraries
  • Clock Tree Synthesis
  • False paths / Multi cycle paths / Critical paths
  • Design for Testability (DFT)
  • Scan Insertion / Types of Scan
  • Fault Models
  • Logic BIST, Memory BIST, ATGP, Boundary Scan
  • Pattern Compression
  • Scan Diagnostics
  • Layout Design
  • Placing and Routing
  • LVS/DRC/OPC/Physical verification
  • Diagnosis, DFM, Yield Analysis
  • SOC Design and Trade-offs
  • Future Trends and challenges
  • ASIC Case Studies

 

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Course Curriculum

VLSI Online Training Introduction

ASIC / FPGA DESIGN

ASIC / FPGA Design Fundamentals

Advanced Digital Design

CMOS

  • MOS Fundamentals and Characterization
  • NMOS/PMOS/CMOS Technologies
  • Fabrication Principles
  • Different Styles of Fabrication for NMOS/PMOS/CMOS
  • Design with CMOS Gates
  • Characterization of CMOS Circuits
  • Scaling Effects
  • Sub-Micron Designs
  • Parasitic Extraction and Calculations
  • Subsystem Design
  • Layout Representation for CMOS Circuits
  • Design Exercise using CMOS
  • Introduction of IC Design
  • Different Methodologies for IC Design
  • Fabrication Flows and Fundamentals

VHDL

  • VHDL Overview and Concepts
  • Levels of Abstraction
  • Entity, Architecture
  • Data Types and declaration
  • Enumerated Data Types
  • Relational, Logical, Arithmetic Operators
  • Signal and Variables, Constants
  • Process Statement
  • Concurrent Statements
  • When-else, With-select
  • Sequential Statement
  • If-then-else, Case
  • Slicing and Concatenation
  • Loop Statements
  • Delta Delay Concept
  • Arrays, Memory Modeling, FSM
  • Writing Procedures
  • Writing Functions
  • Behavioral / RTL Coding
  • Operator Overloading
  • Structural Coding
  • Component declarations and installations
  • Generate Statement
  • Configuration Block
  • Libraries, Standard packages
  • Local and Global Declarations
  • Package, Package body
  • Writing Test Benches
  • Assertion based verification
  • Files read and write operations
  • Code for complex FPGA and ASICs
  • Generics and Generic maps

VERILOG

  • Language introduction
  • Levels of abstraction
  • Module, Ports types and declarations
  • Registers and nets, Arrays
  • Identifiers, Parameters
  • Relational, Arithmetic, Logical, Bit-wise shift Operators
  • Writing expressions
  • Behavioral Modeling
  • Structural Coding
  • Continuous Assignments
  • Procedural Statements
  • Always, Initial Blocks, begin ebd, fork join
  • Blocking and Non-blocking statements
  • Operation Control Statements
  • If, case
  • Loops: while, for-loop, for-each, repeat
  • Combination and sequential circuit designs
  • Memory modeling,, state machines
  • CMOS gate modeling
  • Writing Tasks
  • Writing Functions
  • Compiler directives
  • Conditional Compilation
  • System Tasks
  • Gate level primitives
  • User defined primitives
  • Delays, Specify block
  • Testbenchs, modeling, timing checks
  • Assertion based verification
  • Code for synthesis
  • Advanced topics
  • Writing reusable code

System Verilog

  • Introduction to System Verilog
  • System Verilog Declaration spaces
  • System Verilog Literal Values and Built-in Data Types
  • System Verilog User-Defined and Enumerated Types
  • System Verilog Arrays, Structures and Unions
  • System Verilog Procedural Blocks, Tasks and Function
  • System Verilog Procedural Statements
  • Modelling Finite State Machines with System Verilog
  • System Verilog Design Hierarchy
  • System Verilog Interfaces
  • Behavioral and Transaction Level Modelling
  • FPGA Flow
  • Re-configurable Devices, FPGA’s/CPLD’s
  • Architectures of XILINX, ALTERA Devices
  • Designing with FPGAs
  • FPGA’s and its Design Flows
  • Architecture based coding
  • Efficient resource utilization
  • Constrains based synthesis
  • False paths and multi cycle paths
  • UCF file creation
  • Timing analysis/Floor Planning
  • Place and route/RPM
  • Back annotation, Gate level simulation, SDF Format
  • DSP on FPGA
  • Writing Scripts
  • Hands on experience with industry Standard Tools
  • ASIC Flow

Projects: As a part of course 2 mini projects and 1 major project

  • EDA Tools / CAD Flow for IC Design
  • Simulation/Synthesis using ASIC libraries
  • Clock Tree Synthesis
  • False paths / Multi cycle paths / Critical paths
  • Design for Testability (DFT)
  • Scan Insertion / Types of Scan
  • Fault Models
  • Logic BIST, Memory BIST, ATGP, Boundary Scan
  • Pattern Compression
  • Scan Diagnostics
  • Layout Design
  • Placing and Routing
  • LVS/DRC/OPC/Physical verification
  • Diagnosis, DFM, Yield Analysis
  • SOC Design and Trade-offs
  • Future Trends and challenges
  • ASIC Case Studies

 

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